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d a t a sh eet product speci?cation supersedes data of 1996 sep 13 file under integrated circuits, ic17 1997 jan 28 integrated circuits UMA1002 data processor for cellular radio (dproc2)
1997 jan 28 2 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 features single chip solution to all the data handling and supervisory functions configuration to both amps and tacs additional jtacs option i 2 c-bus serial control all analog interface and filtering functions fully implemented on chip error handling in hardware reduces software requirements robust sat decoding and transponding circuitry low current consumption by on-chip power-down modes reduced system current consumption by new integrated power-saving features C majority voting includes more intelligence C on-chip control filler word filter C bch error filter C possibility to program escc bits small physical size: so28 or lqfp32 external peripheral component count reduced C on-chip selectable clock divider C integrated pull-up resistor at txline simplified reset and abort software routines possible the so28 version is fully compatible with uma1000lt and umf1000t. general description the UMA1002 is a low power cmos lsi device incorporating the data transceiving, data processing, and sat functions (including on-chip filtering) for an amps or tacs hand-held portable cellular radio telephone. in this data sheet, the UMA1002 is often referred to by the descriptive term dproc2. quick reference data ordering information symbol parameter min. typ. max. unit v dd supply voltage 2.7 3.0 5.5 v i dd supply current normal operation with external clock - 1.3 1.8 ma t amb operating ambient temperature - 30 - +70 c type number package name description version UMA1002t so28 plastic small outline package; 28 leads; body width 7.5 mm sot136-1 UMA1002h lqfp32 plastic low pro?le quad ?at package; 32 leads; body 7 7 1.4 mm sot358-1
1997 jan 28 3 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 block diagram b ook, full pagewidth mbd827 clock filter output filter test logic reset, clock and power-down generator 6 (2) 4 (32) 12 (10) (20) 9 (7) 22 (22) 13 (11) st generator manchester and bch encoding i c interface transmit buffer sat regeneration gated d/a gated d/a sat determination bias generator anti- aliasing filter 3 (31) 1 (29) (6) 21 (21) 23 (23) 25 (25) 24 (24) 18 (16) 15 (13) 17 (15) 11 (9) sat filter interpolator sat recovery comparator 2 comparator 1 data recovery arbitration logic 20 (19) syncronization and voting dotting detector error corection 19 (17) 27 (26) 5 (1) 8 (5) (3) 10 (8) 7 (4) 28 (27) (28) tst tscan v dda v ddd invrx recdata mvo rxline rxclk busy/vsat ractrl txctrl tactrl txclk txhold txline scl sda a0 invtx jtacs v ssa 14 (12) v ssd clkout clkin clksel reset data agnd 2 (30) demodd UMA1002 2 fig.1 block diagram. pins in parenthesis apply to UMA1002h in lqfp32.
1997 jan 28 4 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 pinning symbol pin description so28 lqfp32 v ssa 1 29 negative analog supply (0 v). to be connected low-ohmic to v ssd . agnd 2 30 internally generated analog signal ground. voltage level = 1 2 v dda . this pin should be connected to a blocking capacitor, no dc load allowed. demodd 3 31 demodd inputs analog data and sat signals from the rf demodulator. this pin should normally be ac-coupled. see chapter ac characteristics. data 4 32 data is an analog output which provides the manchester encoded and filtered data signal, sat and signalling tone. this signal should normally be ac-coupled into the audio/data summer. see chapter ac characteristics. ractrl 5 1 received audio control output. open-drain output used to blank the audio path to the earpiece when a sequence of dotting followed by a synchronization word or 2 synchronization words separated by 77 bits is detected. ractrl and tactrl functions can be combined using one line. output level low means audio muted. reset 6 2 master reset input resetting all internal ?ip-?ops to the speci?ed state. this input has no in?uence on analog parts, but must be controlled by an active high microcontroller port. invrx 7 4 this input inverts the sense of received data stream, which allows rf demodulators with high or low local oscillators to be used. the amps and tacs speci?cations de?ne nrz encoded logic 1 as a low-to-high transition in the centre of a data bit period. the polarity of the demodulated data stream into dproc2 depends on the receiver local oscillator. input low means data normal. rxline 8 5 received data signal output to the system controller. tst 9 7 test input pin (note 1). recdata 10 8 output of the recovered digital data signal (note 1). tactrl 11 9 transmitter audio control output. this open-drain output is used to blank the audio path and enable the data path to the modulator during data bursts on the rvc. output level low means audio muted. clkin 12 10 1.2 mhz or 9.6 mhz external master clock input. this input signal should be accurate to 100 10 - 6 and have a worst case 60 : 40 mark-space ratio. clkout 13 11 output of 1.2 mhz clock signal (for aproc) derived from clkin. v ssd 14 12 negative digital supply (0 v), internally connected to substrate. to be connected low-ohmic to v ssa . txline 15 13 open-drain bidirectional data line to the system controller (internal 100 k w pull-up). n.c. 16 14 not connected. txhold 17 15 this input holds off transmission of data when set to high. txclk 18 16 transmitted data clock input from the system controller. busy/vsat 19 17 output indicating the status of the recc by providing output information based on a majority decision on the last 3 consecutive busy/idle bits (fvc = logic 0). output level low means channel idle. indicating the result of the comparison of the measured sat and the expected sat colour-code bits (i 2 c-bus register) in the voice channel mode (fvc = logic 1 and ensm = logic 1). output level low means incoming sat not equal to expected sat.
1997 jan 28 5 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 note 1. must not be connected in existing applications. txctrl 20 19 transmitter control open-drain output used to disable the transmitter during an recc access failure. output level low means rf disabled. invtx 21 21 this input inverts the sense of transmitted data stream, which allows rf modulators with high or low local oscillators to be used. the amps and tacs speci?cations de?ne nrz encoded logic 1 as a low-to-high transition in the centre of a data bit period. the polarity of the modulated data stream depends on the transmitter local oscillator. input low means data inverted. tscan 22 22 test switch input, only enabled if tst = logic 1, but should have a de?ned state. a0 23 23 input to select the least signi?cant bit of the i 2 c-bus address. sda 24 24 serial data input/output (i 2 c-bus). scl 25 25 serial clock input (i 2 c-bus). n.c. 26 18 not connected. rxclk 27 26 received data clock input from the system controller. v ddd 28 27 digital supply voltage (+3 v). v dda - 28 analog supply voltage (+3 v). mvo - 3 majority voting output indicating that on focc the ?rst 3 received words do not differ from each other and thus the majority decision over 5 words can already be carried out. because of the required speed, indication is at this pin (and not via the i 2 c-bus) which can be monitored by the system controller. output low means the receiver can be switched off. jtacs - 6 digital input signal for jtacs, input high means that data is routed from txline directly without processing to gated d/a converter (if enabled by sten bit). clksel - 20 input switch for internal divide-by-8 or divide-by-1 divider between clkin and clkout (internal pull-down ? divide-by-1 is default if not bonded out in so28 package). symbol pin description so28 lqfp32
1997 jan 28 6 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 fig.2 pin configuration for so28, sot136-1. handbook, halfpage 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 v ssa v ssd agnd demodd data ractrl reset invrx rxline tst recdata tactrl clkin clkout v ddd rxclk scl sda a0 tscan invtx txctrl busy/vsat txclk txhold n.c. txline mbd828 UMA1002t n.c. fig.3 pin configuration for lqfp32, sot358-1. handbook, full pagewidth 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 sda a0 tscan invtx clksel txctrl n.c. busy/vsat tactrl clkin clkout txline n.c. txhold txclk ractrl reset mvo invrx rxline jtacs tst recdata UMA1002h data demodd agnd v v v rxclk scl ssa v ssd dda ddd mbd829
1997 jan 28 7 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 functional description general the UMA1002 (dproc2) is a single-chip cmos device which handles the data and supervisory functions of an amps or tacs subscriber set. these functions are: data reception and transmission control and voice channel exchanges error detection, correction, decoding and encoding supervisory audio tone decoding and transponding signalling tone generation. in an amps or tacs cellular telephone system, mobile stations communicate with a base over full duplex rf channels. a call is initially set up using one out of a number of dedicated control channels. this establishes a duplex voice connection using a pair of voice channels. any further transmission of control data occurs on these voice channels by briefly blanking the audio and simultaneously transmitting the data. the data burst is brief and barely noticeable by the user. a data rate of 10 kbits/s is used in the amps system and 8 kbits/s in tacs. the signalling formats for both forward channels (base to mobile) and reverse channels (mobile to base) are shown in fig.14. a function known as supervisory audio tone (sat), a set of 3 audio tones (5970, 6000 and 6030 hz), is used to indicate the presence of the mobile on the designated voice channel. this signal, which is analogous to the on-hook signal on land lines, is sent out to the mobile by the base station on the forward voice channel. the signal must be accurately recovered and transponded back to the base station to complete the loop. at the base station this signal is used to ascertain the overall quality of the communication link. another voice channel associated signal is signalling tone (st). this tone (8 khz tacs, 10 khz amps) is generated by the mobile and is sent in conjunction with sat on the reverse voice channel to serve as an acknowledgement signal to a number of system orders. the key requirements of a hand-held portable cellular set are: small physical size minimum number of interconnections (serial bus) low power consumption low cost. the dproc2 is a member of our cellular radio chip set, based on the i 2 c-bus, which meets these requirements. a cellular radio system schematic using the chip set is shown in fig.11. dproc2 power-saving features to support current saving in the application, dproc2 has three different modes of circuit operation implemented. they are decoded by the i 2 c-bus register bit fvc and by activity on the data transfer link (txclk and txline). in power-down mode the relevant digital circuits have the clock disabled, the analog circuits have the bias currents and the switched capacitor clock switched off. normal mode: all circuit parts are operating (e.g. on voice channels) power-down mode 1: the sat path is in power-down (e.g. during access of the recc) power-down mode 2: the sat path and the total data transmit path are in power-down (e.g. for idle state, dproc2 operating only on focc). system power-saving features besides the above mentioned power-down modes dproc2 also includes features to reduce system current (e.g. switching off parts of the receiver, and put the system controller into idle mode for longer periods of time). all these features are controlled by the i 2 c-bus. for further explanation of the following features refer to the section i2c-bus serial data link (sda; scl) sub-section i2c-bus registers. m ajority voting ( only in lqfp 32) majority voting includes more intelligence. this feature is enabled in focc with i 2 c-bus bit maj = logic 1. if 3 consecutive identical words have been received it is signalled via pin mvo. therefore during the last 2 frame words the receiver could be switched off to save system current consumption. c ontrol filler words filter system current can be further reduced by an on-chip control filler words filter in focc, which enables the detection of consecutive identical control filler words. if consecutive control filler words are identical (i.e. dcc, cmac and wfom) they will not be passed on to the microcontroller. consequently the system controller can remain in power-saving mode.
1997 jan 28 8 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 p rogramming of escc bits there is a possibility to program the expected escc bits, so that dproc2 can compare expected and received sat and signal any inconsistency to the system controller via busy/vsat pin. consequently there is no need to read the measured sat periodically via the i 2 c-bus. bch error filter if this feature is enabled, dproc2 will not pass on to the microcontroller words with bch errors. consequently the microcontroller can remain in power-saving mode. this feature in combination with the control filler feature is defined in table 8. s electable clock divider ( only in lqfp32) an on-chip selectable divide-by-8 clock divider reduces external peripheral component count. power-up state and master reset (reset) reset should be high as soon as power supply is available. dproc2 will not respond reliably to any inputs (including reset) until 100 m s after the power supply has settled within the specified tolerance. the analog sections of the device will have stabilized within 5 ms. no on-chip power-on reset is provided, therefore before the device can enter normal operation reset must be held high. reset is an active high master reset input, with a minimum active pulse width of 4 m s which may be used to reset the total logic within dproc2 to a predefined state as illustrated in tables 1 and 2. it is preferably only used during power-up, during normal operation it is recommended to use the fully synchronous reset signals derived from the i 2 c-bus bits fvc, sts and txrst (see table 4). to ensure correct operation txclk must be held high during reset operation. table 1 prede?ned state of the digital output pins table 2 prede?ned state of the i 2 c-bus registers output state rxline high txctrl high-impedance (high) tactrl high-impedance (high) ractrl high-impedance (high) busy/vsat high txline high (by 100 k w internal pull-up resistor) recdata low mvo high sda high-impedance (high) register bit 76543210 status (read) low low low high low low high high control 1 (write) low low low low low low low low control 2 (write) low low low low low low low low
1997 jan 28 9 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 i 2 c-bus serial data link (sda; scl) sda is the bidirectional data line, scl is the clock input from an i 2 c-bus master. these constitute a typical i 2 c link and conform to standard i 2 c-bus characteristics. a detailed description of the i 2 c-bus specification, with applications, is given in the brochure the i 2 c-bus and how to use it. this brochure may be ordered using the code 9398 393 40011. data rate up to 100 kbits/s. s lave address select (a0) selection of the device slave address is achieved by connecting a0 to either v ss or v ddd . the slave address is defined in accordance with the i 2 c-bus specifications as shown in fig.4. fig.4 device slave address. handbook, halfpage mbd831 r/w 11011 x a0 (1) (1) x = dont care. i 2 c- bus registers the i 2 c-bus register block resides internally within the i 2 c-bus interface block and contains various items of status and control information which are transferred to and from dproc2 via the i 2 c-bus. the block is organized into three 8-bit registers: status register which contains read only items control registers 1 and 2 which contain write only items. table 3 i 2 c-bus register map register bit 76543210 status (read) -- wsync busy txabrt txip mscc1 mscc0 control 1 (write) bufen serv sts txrst abren fvc sten saten control 2 (write) maj mr1 mr0 dbch dcfm ensm escc1 escc0
1997 jan 28 10 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 fig.5 i 2 c-bus data format. (a) read from dproc2 status register. (b) write to dproc2 control register 1. (c) write to all dproc2 control registers. where: s = start condition w = read/write bit (logic 0 = write) r = read/write bit (logic 1 = read) a = acknowledge bit p = stop condition dproc adr = slave address of dproc2. handbook, full pagewidth mbd832 dproc adr s r a status control 1 p wa a p dproc adr s control 1 wa a dproc adr s control 2 a p (a) (b) (c)
1997 jan 28 11 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 table 4 description of i 2 c-bus register map register bits logic level description control register 1 bufen 0 1.2 mhz signal not available at pin clkout 1 1.2 mhz signal is available at pin clkout serv 0 serving system data stream b selected 1 serving system data stream a selected sts (1) 0 tacs selected 1 amps selected txrst 1 terminates a message being transmitted on the reverse channel; monostable signal causing a reset of the message transmission circuitry and resets the i 2 c-bus bits txabrt, txip and clears the transmit buffer abren 1 dproc2 has permission to abort data transmission and disable rf on the recc following the detection of a channel access attempt collision 0 no permission for above operations fvc (2) 0 control channel format selected 1 voice channel format selected sten 0 disables output of signalling tone to pin data 1 enables output of signalling tone to pin data if fvc = logic 1 saten 0 disables output of sat transponded signal to pin data 1 enables output of sat transponded signal to pin data if fvc = logic 1 control register 2 maj 0 majority voting procedure on focc using all 5 frame words, mvo output is always high 1 majority voting procedure on focc using the ?rst 3 frame words, if they are all identical the mvo pin goes low (see fig.6) mr0, mr1 see table 5 determines set-up time of mvo signal with respect to beginning of the next dotting (see fig.6) dbch see table 8 bch error ?lter dcfm see table 8 control ?ller message ?lter ensm 0 enable sat monitoring; escc bits are not used 1 enable sat monitoring; escc bits are used for following function escc0, escc1 see table 6 expected sat colour code bits; the incoming sat is compared to these bits, the result (expected or not expected sat frequency) is given out by the busy/vsat pin (when fvc = logic 1), which prevents periodical reading from the i 2 c-bus status register status register wsync 0 dproc2 has not acquired frame synchronization in accordance with focc format 1 dproc2 has acquired frame synchronization in accordance with focc format
1997 jan 28 12 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 notes 1. changing this register bit resets internally the receive and transmit logic circuitry. 2. changing this register bit resets internally the receive logic circuitry. busy indicates the status of recc, determined by a majority decision on the result of the last 3 consecutive busy/idle bits of the focc and is also routed to pin busy/vsat 0 channel idle 1 channel busy indicates the result of the comparison of the incoming sat and the stored sat colour code bits in the voice channel mode and is also routed to pin busy/vsat 0 incoming sat not equal to expected sat 1 incoming sat equal to expected sat txabrt indicates that a recc access attempt has been aborted without successful message transmission 0 no access collision detected 1 transmission attempt aborted txip 0 no transmission on recc or rvc in progress 1 data transmission by dproc2 on recc or rvc in progress mscc1, mscc0 see table 7 provides information about the current measured sat colour code register bits logic level description table 5 set-up time of mvo signal table 6 expected sat colour code mr0 mr1 t mvo (ms) 003 016 109 1112 escc1 escc0 sat frequency (hz) 0 0 5970 0 1 6000 1 0 6030 1 1 no valid sat table 7 measured sat colour code mscc1 mscc0 sat frequency (hz) 0 0 5970 0 1 6000 1 0 6030 1 1 no valid sat
1997 jan 28 13 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 table 8 conditions for transmission of received words to system controller dbch dcfm bch error bit change in control filler word detected transmission of control filler word to system controller 0 0 x x yes 010 0 no 010 1 yes 011 x yes 100 x yes 101 x no 110 0 no 110 1 yes 111 x no fig.6 timing of mvo output. handbook, full pagewidth mlc095 bit sync repeat 1 of word a bit sync word sync repeat 1 of word b repeat 2 of word a repeat 2 of word b repeat 3 of word a repeat 3 of word b repeat 5 of word b t mvo mvo
1997 jan 28 14 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 digital circuit blocks g eneral the majority of the digital circuitry within the dproc2 device is identical for both amps and tacs. the interconnections of the digital blocks discussed below are shown in fig.1 . d ata r ecovery the data recovery block receives wideband manchester encoded data in sampled and sliced form from the comparator block, on which it performs the following functions: clock recovery manchester decoding data regeneration. the clock recovery block extracts an 8 or 10 khz (tacs or amps) phase-locked clock signal from the manchester encoded data stream. this is implemented using a digital-phase-locked-loop (pll) which has an adjustable bandwidth to provide both fast acquisition and low jitter. manchester decoding is performed by exclusive oring the recovered manchester encoded data with the recovered clock. the nrz data regeneration is performed by a digital integrate and dump circuit. this consists of an up/down counter that counts 1.2 mhz cycles during the data period. the sense of the count is determined by the result of the manchester decoder output. the number of counts is sampled at the end of a data period. if this number exceeds a threshold the data is latched as a logic 1 otherwise it is latched as a logic 0. sat recovery the sat recovery block receives a filtered and sliced sat signal which must be recovered before being routed to the determination and regeneration blocks. the recovery is performed using a digital phase-locked loop. sat determination the sat determination block indicates which, if any, of the valid sat tones is detected from the recovered sat. the amps and tacs specifications require that a determination is made at least every 250 ms. determination involves counting the number of cycles of the regenerated sat in this time period. this count is then compared to a set of four known counts which define the boundaries between the sat frequencies and sat-not-valid events. the result is then coded into the i 2 c status registers mscc0 and mscc1. sat regeneration the sat regeneration block generates a digital sat stream for transponding back to the base station. the transponded sat is phase-locked to the recovered sat by means of a second digital phase-locked-loop. to minimize the total harmonic distortion of the output signal the transponded sat is then processed by a delta modulator before being passed on to the gated digital-to-analog (d/a) converter. d otting d etector the dotting detector block determines whether a data inversion (dotting) pattern has been received on the forward voice channel. the detection of data inversion indicates that the clock recovery block has acquired bit synchronization and that the narrow bandwidth mode on the clock recovery phase-locked-loop is selected. this signal is also used to indicate that a data burst is expected and activates the audio mute ractrl, after a word synchronization block has been received, for the duration of the burst.
1997 jan 28 15 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 w ord s ynchronization d etector the word synchronization block performs the following functions: frame synchronization reverse control channel status (b/i determination) valid serving system determination. these functions are associated solely with the forward control channel and have no meaning on the forward voice channel. information in a data stream is identified by its position with respect to a unique synchronization word. this synchronization word is an 11-bit barker code which has a low probability of simulation in an error environment, and can be easily detected. data received is only considered valid at times when dproc2 has achieved frame synchronization. in this condition the block leaves its search mode and enters its lock mode. this is indicated by bit wsync being set high. in order to achieve this two consecutive synchronization words separated by 463 bits must be detected. once in lock mode, the synchronization word detector is examined every 463 bits and only loses frame synchronization after 5 consecutive unsuccessful attempts at detecting the synchronization word have been made. at this point bit wsync is cleared and the device is returned to its search mode. information detailing the status of the reverse control channel is given by the busy/idle bits. these occur at intervals of 11 bits within the frame, the first occurring immediately following the synchronization word. the status of the channel is determined by a majority decision on the last three consecutive busy/idle bits. fvc: after detection of 2 consecutive sync words the circuit leaves its search mode and enters the lock mode. the data word in between is considered as valid and already stored for majority voting. whenever a sync word was found the incoming data stream is examined 88 bits later for sync again. whenever a valid sync word is detected the following data word is given to the majority voting block. after missing two consecutive sync words the circuit goes back to the search mode (scanning for sync every bit). if a sync word is then detected again, the following data word is immediately accepted (and not only after two correctly timed sync words). the detection process of sync words is independent of the detection of dotting. the audio mute via pin ractrl is activated either by receiving a sync word after detection of a dotting sequence or by entering lock mode. m ajority v oting b lock the majority voting block performs the following functions: identifying position and validity of frames in the received data stream extracting five repeats of each word from a valid frame performing a bit-wise majority decision on the five repeats of the data word. the validity of the frames is determined by setting a counter in operation which times out and resets the circuitry after 920 or 463 bit periods from detecting valid word synchronization. the time out period selected depends on whether dproc2 is monitoring the forward voice or control channel respectively. up to five repeats of the message word are searched for and extracted by dproc2. on the forward voice channel the extraction of a data word for majority voting is described in the section word synchronization detector. dproc2 enables two mechanisms for majority voting. the first is based on 5 words and is described above. the other mechanism is based on 3 consecutive identical words and thus enabling switch-off of parts of the receiver during reception of the remaining two words (see table 5 and fig.6). e rror c orrection b lock the error correction block performs: extraction of a valid message from the majority-voted word computation of the s1 and s3 syndromes correction of up to one error in the word communication of received data to the system controller via the received data serial link. interpretation of parity of a received word is obtained from knowledge of the syndromes of the word. the syndromes are calculated using feedback shift registers with two characteristic polynomials: 1+x+x 6 and1+x+x 2 +x 4 +x 6 once the syndromes of a received word are known, it is possible to determine if a correctable error is present. dproc2 only corrects up to one error although the code used has a hamming distance of five. the occurrence of two or more errors is signalled by setting the bch error flag, which is communicated to the system controller via the received data serial link.
1997 jan 28 16 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 r eceived d ata s erial l ink the received data serial link transfers data and control information from dproc2 to the system controller. the data is transferred on rxline under control of a clock signal rxclk, generated by the system controller. the system controller is informed of the arrival of a decoded data word in the dproc2 output register by rxline being driven low. if the system controller chooses to ignore the received data or only partially clock the data out, the dproc2 will reset the receive buffer for the next word after the period rwin (see fig.8). data format each received data word consists of 4 bytes. the word format is shown in fig.7(a). the sense and function of the fields is shown in table 9. link protocol the received data protocol is described by the timing diagram fig.8(a) and has the following parameters: maximum receive window (rwin) C control channel (tacs) = 47 ms; maj = 0 C control channel (tacs) = 30.5 ms; maj = 1 (in focc only) C control channel (amps) = 37 ms; maj = 0 C control channel (amps) = 23.8 ms; maj = 1 (in focc only) minimum clock period (t clkmin )=2 m s minimum clock hold-off (t wait )=2 m s. t ransmit d ata s erial i nterface the transmit data serial link performs reception of data from the system controller to dproc2 over a dedicated line txline. the transfer of data is synchronous with a clock signal txclk, generated by the system controller. data format each transmit data word consists of 5 bytes. the word format is shown in fig.7(b). the sense and function of the fields is shown in table 10. link protocol messages are normally up to 5 words in length on the reverse control channel and up to 2 words in length on the reverse voice channel. however, dproc2 will transmit messages of any word length. these must be transmitted on the data stream without interruption. to avoid the need for large buffer areas, a flexible protocol is used to allow dproc2 to control the transfer of data words. dproc2 has an on-chip buffer which can hold one complete word of a message. while new words are being loaded into dproc2, within the time period buffer clear to end of twin, dproc2 will maintain uninterrupted data transmission. the system controller can abort the transmission of a message at any point activating the i 2 c-bus signal txrst. this signal causes the interface to return to its power-up state and resets txip and txabrt (see table 4). on completion of these tasks txrst will return to its inactive state. the transmit data protocol is described by the timing diagram shown in fig.8(b) and has the following parameters: maximum transmit window (twin) C voice channel (tacs) = 60 ms C voice channel (amps) = 48 ms C control channel (tacs) = 29 ms C control channel (amps) = 23 ms minimum clock period (t clkmin )=2 m s minimum wait period (t wait )=2 m s. note that txrst will clear the transmit buffer.
1997 jan 28 17 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 table 9 received data word table 10 transmit data word bit title sense function 31 start low identi?es start of word 30 bch error active high indicates that an uncorrected bch error is associated with the word 29 to 2 received data binary data received data word 1 rxline error active high indicates that a transmission error has occurred on the microprocessor to dproc2 serial link 0 stop high identi?es end of the word bit title sense function 39 start low identi?es start of word 38 and 37 dcc binary data digital colour code (see table 11) 36 to 1 transmit data binary data transmit data word 0 stop high identi?es end of the word fig.7 data word formats. (a) received data word. (b) transmit data word. handbook, full pagewidth mbc768 start bch error start dcc 1 dcc 0 received word (28 bits) transmit word (36 bits) check bit (= 0) stop stop lsb lsb bit 1 bit 0 bit 2 bit 29 bit 30 bit 31 bit 36 bit 38 bit 39 bit 37 bit 1 bit 0 msb msb (a) (b)
1997 jan 28 18 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 fig.8 data timing diagrams. (1) the buffer time depends on whether the first or subsequent words are being loaded. (2) the system controller should monitor the txline during bit 0, if the status of txline does not change from a high-to-low on t he rising edge of txclk, then a framing error has occurred. this can be caused by glitches on the clock line or if an arbitration error occurred while the dproc2 transmit register was being loaded. the system controller should recover the situation by holding txline high and supplying clo cks on txclk until txline goes low. then the situation should be treated as a normal channel arbitration failure as described in section re verse control channel access arbitration - abort procedure (see fig.10). (a) dproc2 to microcontroller link; receive data timing. (b) microcontroller to dproc2 link; transmit data timing. where: t h > 100 ns t su > 500 ns. handbook, full pagewidth mbc769 bit 31 bit 30 bit 29 bit 2 bit 1 bit 0 rwin t clk (min) t wait rxline rxclk bit 39 bit 38 t h t su txline txclk bit 1 bit 0 buffer busy (1) (2) buffer clear dproc holds txline low during encoder stage t wait twin (a) (b)
1997 jan 28 19 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 bch and m anchester e ncoding b lock the functions performed by this circuit block include: reception of data from the system controller parity generation message construction manchester encoding. each 36-bit information word sent on the reverse voice and control channels is coded into a 48-bit code word. the code word consists of the 36-bit word followed by 12 parity bits. these parity bits are formed by clocking the information word into a 12-bit feedback shift register with characteristic polynomial: 1+x 3 +x 4 +x 5 +x 8 +x 10 +x 12 the bch encoder block constructs the reverse voice and control channel data streams from the information it receives from the system controller. the streams are formed out of the four possible field types: dotting (data inversions) 11-bit synchronization word digital colour code (see table 11) 48-bit code word. the 2 bits of dcc received from the system controller are coded into a 7-bit word as shown in table 11. the data sense for manchester encoding has a nrz logic 1 encoded as a 0-to-1 transition and a nrz logic 0 encoded as a 1-to-0 transition. r everse c ontrol c hannel a ccess a rbitration the amps and tacs specifications require a method of arbitration on the reverse control channel to prevent two mobiles from transmitting on the same channel at the same time. this function is performed by dproc2 monitoring the busy/idle stream sent on the forward control channel. the amps and tacs specifications state that once the mobile has commenced transmitting on the reverse control channel it must monitor the busy/idle stream. if this stream becomes active outside a predetermined window, measured from the start of the transmission of the message, the mobile must terminate its transmission and disable the transmitter immediately. in the cellular radio chip-set there are two levels of control of the rf transmitter; the first is absolute control by the system controller, the second is conditional by other devices in the set. in dproc2 the conditional control of the transmitter is performed via the output txctrl. this line is effectively wired ored together, using open-drain outputs, with other devices which may wish to control the transmitter. when these devices do not wish to disable the transmitter their output is in a high impedance state. an exception to this procedure occurs when the serving system instructs the mobile not to monitor the busy/idle bits. in this event the arbitration logic can be disabled by clearing i 2 c-bus register bit abren. the flow of events during a control channel access attempt is as follows: initial state transmitter disabled dproc2 transmit circuitry in power-up state txctrl line high. table 11 digital colour code; 7-bit word dcc1 dcc0 coded dcc 000000000 010011111 101100011 111111100
1997 jan 28 20 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 access attempt procedure 1. system controller decides to send message (1) . 2. system controller drives txctrl low directly. 3. system controller switches transmitter power-on and waits for power-up for the transmitter module (rf transmitter is still disabled by txctrl). 4. system controller sets txrst via i 2 c-bus to dproc2. 5. system controller sets abren via i 2 c (if required) allowing dproc2 to control the transmitter. 6. system controller determines status of reverse control channel by monitoring the busy/idle bit. if busy, waits a random time then tries again. 7. system controller releases txctrl allowing it to be pulled high enabling the transmitter output. 8. system controller transfers the first word of the message to dproc2 via serial link (1) . 9. dproc2 sets i 2 c-bus signal txip and starts sending message while monitoring busy/idle status. 10. if channel becomes busy before 56 bits and abren is set then perform abort procedure. 11. if channel remains idle after 104 bits and abren is set then perform abort procedure. 12. system controller loads the subsequent words of the message into dproc2 when the buffer becomes clear as shown in fig.8(b). 13. on completion of entire message dproc2 clears txip and 25 ms later the system controller disables transmitter via i 2 c-bus. 14. system controller finally sends txrst to prepare dproc2 for next transmission. (1) at stage 1 the system controller may choose to preload dproc2 with the ?rst word of the message and hold it from transmission until stage 7 using the txhold line. this gives a lower time overhead between detecting an idle channel and commencing the transmission. to use this feature txhold must be driven high before the last bit of data has been transferred into dproc2. figure 9 illustrates the dproc2 data transmission timing. abort procedure (see fig. 10 ) 1. dproc2 immediately disables transmitter output by driving txctrl low. 2. dproc2 sets txabrt. 3. system controller detects failure by monitoring txctrl and txabrt. 4. system controller disables transmitter via rf power amplifier. 5. system controller sends txrst to prepare dproc2 for next transmission. s ignal t one g eneration (st) the 8 or 10 khz (tacs or amps) tone generated from the manchester encoding block is used as the signalling tone stream.
1997 jan 28 21 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 fig.9 dproc2 data transmission timing/microcontroller interface. handbook, full pagewidth dotting w.s. dcc word 1 repeat1 36 word 1 repeat 2 36 30 11 7 parity 12 txline txhold dproc2 data word 1 word 2 dproc2 holds low txline dproc2 releases txline dproc holds low txline parity 12 word 1 repeat 5 36 parity 12 word 3 dproc2 releases txline word 2 repeat 1 36 word 2 repeat 2 36 parity 12 dproc2 holds low txline parity 12 parity 12 word 4 word 2 repeat 5 36 word 3 repeat 1 36 parity 12 parity 12 txline continued txhold continued dproc2 data continued word n repeat 1 36 word n repeat 2 36 parity 12 parity 12 parity 12 word n repeat 5 36 parity 12 txline continued txhold continued dproc2 data continued mea173
1997 jan 28 22 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 fig.10 dproc data transmission timing/microcontroller interface during arbitration failure. handbook, full pagewidth i 2 c-bus mea172 dotting w.s. dcc word 1 repeat1 36 word 1 repeat 2 truncated 30 11 7 parity has to be controlled by system controller 12 104 bits txline txip txabrt txhold txctrl busy dproc2 data word 1 word 2 dproc2 holds low txline dproc2 releases txline dproc2 holds low txline arbitration failure busy/idle stream remains idle after 104 bits dproc2 ready for new transmisson send txrst to dproc2 i 2 c-bus
1997 jan 28 23 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 analog circuit blocks g eneral the analog signal processing functions on dproc2 are implemented using switched-capacitor techniques. the main filtering functions are operated at 300 khz, and these circuits are interfaced to the continuous time and sampled digital domains by rc active filters, passive interpolators and comparators. the rc sections, the anti-alias filter and the clock filter, are non-critical and are designed to tolerate process spreads. the critical filtering in the sat filter and the output filter, is performed by 300 khz switched-capacitor circuitry. the passive interpolator increases the sampling rate from 300 khz to 1.2 mhz. the sampled analog signals from the passive interpolator is converted to a sampled 2-state digital signal by a comparator. the gated d/a converter blocks and analog summer block together perform resynchronization and sub-sampling of the digitally generated dproc2 output signals, and conversion to the sampled analog domain. these analog sections of the device are shown in fig.1. b ias g enerator the bias generator generates the analog ground reference voltage (agnd) used internally within the dproc2 device. to minimize noise agnd must be externally decoupled to v ssa as shown in fig.12. it also contains a current reference to generate all bias currents for the analog circuits. a nti -a liasing f ilter the anti-aliasing filter is placed before the sat filter block to prevent any unwanted signals or high-frequency noise present on the demodd pin being aliased into the pass-band by the sampling action of the switched-capacitor filter. to achieve this the anti-aliasing filter is a time-continuous rc-active low-pass filter. sat i nput f ilter the sat input filter is a switched-capacitor filter which provides band-pass filtering of the sat signals from the demodd pin to improve the sat signal-to-noise ratio prior to recovery and transponding. p assive i nterpolator the function of the passive interpolator is to increase the sampling rate at the output of the sat filter. this reduces the coarseness of the zero-crossing information which would otherwise cause unacceptable isochronous distortion in the recovered signal. c omparators the comparators form the analog-to-digital interface for the received data and sat signals from the demodd pin. these comparators act as limiting amplifiers which convert the filtered sampled analog signals into 2-state sampled digital signals containing only the zero-crossing information from the analog signal. to prevent unwanted signals being processed by the digital circuitry both comparators have a hysteresis implemented g ated d/a converters and a nalog s ummer the gated d/a converters and analog summer form the interface between the digital and analog circuitry on the transmit path of dproc2. it is at this point that the three sampled digital signals, containing sat, st and encoded digital data, are combined to form a composite signal. the data streams are enabled by the i 2 c signals sten, saten and the internal signal dataen respectively (dataen disables sat and st when data is being transmitted). the digital-to-analog conversion and sub-sampling operation is performed by the gated d/a converters and analog summer. the typical relative signal weights applied in the summer (with respect to the data path) are shown in table 12. table 12 typical relative signal weight o utput f ilter the output filter is a switched-capacitor filter which performs band-limiting of the dproc2 output signals in accordance with the amps and tacs specifications. the required below band roll-off is achieved via external ac-coupling from the data pin. c lock f ilter the clock noise filter is a non-critical continuous time rc-active low-pass filter used to remove any switching transient residues from the output signal. it contains an output driver stage to provide a low output impedance and sufficient driving capability for the pin data. signal relative output level amps and tacs st or data 1.0 sat 0.25
1997 jan 28 24 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 application information b ook, full pagewidth mbd830 quad tank second if ne606 vco ne620 or discrete solution uma1015 vco rssi demod data 1.2 mhz UMA1002 p83cl580 ne5753 1.2 mhz ne5752 tda7050 mod power control 5 v pa bgy118a/b bgy115a/b i c bus 2 5 v dc-dc 3 v chip-on-glass lcd keyboard scan bus 3-wire control bus tcxo 9.6 mhz power control psd312l fig.11 cellular radio system schematic for amps/tacs.
1997 jan 28 25 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 a ndbook, full pagewidth modout clkin modulation transmitter subsystem receiver subsystem 1.2 mhz output 100 nf 10 m f v ddd 3 v) ( 2.2 m f i 2 c interface microcontroller (pcb80c552) general purpose i/o ports sda scl busy/vsat rxline rxclk txline txclk txhold n.c. tscan a0 data txctrl tactrl ractrl clkin clkout invrx invtx tst v ssa agnd demodd 100 k w 100 nf n.c. 10 3 2 1 v ssd 9 14 21 7 13 12 420115 23 22 16 6 17 18 15 27 8 19 28 24 25 reset 10 nf 10 nf vox demod agnd data tx mute rx mute audio processor 1.2 mhz txdis data processor UMA1002t demodulated data/audio 270 pf line mbd833 v ddd ( + 3 v) ( + 3 v) recdata + + fig.12 dproc2 baseband application circuit (so28, sot136-1).
1997 jan 28 26 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 handbook, full pagewidth modout clkin modulation transmitter subsystem receiver subsystem 9.6 mhz output 100 nf 10 m f v ddd ( + 3 v) v dda ( + 3 v) 2.2 m f i 2 c interface microcontroller (pcb80c552) general purpose i/o ports sda scl busy/vsat rxline rxclk txline txclk txhold n.c. tscan a0 data txctrl tactrl ractrl clkin clkout invrx invtx tst v ssa agnd demodd 100 k w 100 nf 8 31 30 29 v ssd 7 mvo 3 12 21 4 11 10 32 19 9 1 23 22 14,18 2 6 15 16 13 26 5 17 27 24 28 25 reset jtacs 10 nf 10 nf demod agnd data tx mute rx mute audio processor 9.6 mhz 1.2 mhz txdis data processor UMA1002h demodulated data/audio 270 pf line mgc630 v ddd ( + 3 v) clksel 20 ( + 3 v) ( + 3 v) recdata + + vox fig.13 dproc2 baseband application circuit (lqfp32, sot358-1).
1997 jan 28 27 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 signalling formats a ndbook, full pagewidth (a) (b) (c) bit sync word sync repeat 1 of word a repeat 1 of word b repeat 2 of word a repeat 4 of word a repeat 4 of word b bit sync repeat 5 of word a repeat 5 of word b 10 11 40 40 40 40 40 40 40 10 busy/idle bit bit sync word sync repeat 1 of word 101 11 40 37 bit sync word sync repeat 2 of word 11 37 bit sync word sync 11 40 repeat 9 of word 37 bit sync word sync 11 40 repeat 10 of word 40 37 bit sync word sync repeat 11 of word 11 40 bit sync word sync coded dcc first word repeated 5 times second word repeated 5 times 30 11 7 240 240 (d) mbc770 bit sync word sync repeat 1 of word 1 101 11 48 bit sync word sync repeat 2 of word 1 37 11 48 bit sync word sync 37 11 repeat 5 of word 1 48 bit sync word sync repeat 1 of word 2 37 11 48 bit sync word sync 37 11 repeat 5 of word 2 48 fig.14 signalling formats. (a) focc (forward control channel). (b) fvc (forward voice channel). (c) recc (reverse control channel). (d) rvc (reverse voice channel).
1997 jan 28 28 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 limiting values in accordance with absolute maximum rating system (iec 134). symbol parameter conditions min. max. unit v dd supply voltage - 0.5 +6.5 v i dd supply current - 50 ma i i dc input current (any input) - 10 ma i o dc output current (any output) - 10 ma v i input voltages (all inputs) v dd(max) =6v - 0.5 v dd + 0.5 v p tot total power dissipation - 300 mw p o power dissipation per output - 10 mw t amb operating ambient temperature - 30 +70 c t stg storage temperature - 65 +150 c
1997 jan 28 29 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 dc characteristics v dd = 3 v (v dda and v ddd externally connected); t amb = - 30 to +70 c; f clkin = 1.2 mhz (if clksel = logic 0); unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v dd supply voltage 2.7 3.0 5.5 v i dd operating supply current at pins v ddd and v dda in fvc - 1.3 1.8 ma in focc - 0.4 - ma digital inputs: invrx, invtx, clksel, txhold, txclk, a0, reset, rxclk, tst, tscan, clkin and jtacs v il low level input voltage - 0.3 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd + 0.3 v i li low/high level input leakage current pins without pull-down -- 1 m a r pdclksel clksel internal pull-down resistance - 200 - k w r pdjtacs jtacs internal pull-down resistance - 200 - k w r pdtst tst internal pull-down resistance - 200 - k w digital push-pull outputs: rxline, busy/vsat, recdata, mvo and clkout v ol low level output voltage i sink =1ma -- 0.4 v v oh high level output voltage i source = - 1ma v dd - 0.4 -- v open-drain n-channel outputs: txctrl, tactrl and ractrl v ol low level output voltage i sink =2ma -- 0.4 v open-drain n-channel input/output: txline v ol low level output voltage i sink =2ma -- 0.4 v v il low level input voltage - 0.3 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd + 0.3 v r putxline internal pull-up resistance - 100 - k w i 2 c-bus pins: scl and sda t data data conversion rate -- 100 kbits/s analog reference pin: agnd v agnd dc voltage level for v dd = 2.7 to 5.5 v - 0.5v dd - v
1997 jan 28 30 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 ac characteristics v dd = 3 v (v dda and v ddd externally connected); t amb = - 30 to +70 c; f clkin = 1.2 mhz (if clksel = logic 0); unless otherwise speci?ed. note 1. plus supply voltage variation ( d v dd ), r l =10k w . symbol parameter conditions min. typ. max. unit data rate of data transfer link: rxclk, rxline, txclk, txline t data data conversion rate -- 500 kbit/s clock input: clkin (clksel = logic 0) c i input capacitance - 5 - pf t clkin clock input period time 833.25 833.33 833.42 ns t clkinh clock input high time 40 50 60 %t clkin t r clock input rise time - 50 - ns t f clock input fall time - 50 - ns clock input: clkin (clksel = logic 1) t clkin clock input period time - 104.17 - ns t clkinh clock input high time 40 50 60 %t clkin t r clock input rise time - 5 - ns t f clock input fall time - 5 - ns analog output: data v data dc output voltage level - v agnd - v v o(p-p) output voltage level for signalling tone (peak-to-peak value) v dd = 3 v; note 1 1.14 1.2 1.26 v v dd = 5 v; note 1 1.9 2.0 2.1 v thd total harmonic distortion for supervisory audio tone (sat) -- 10 % r l allowed load resistance to ac ground 10 -- k w c l allowed load capacitance to ac ground -- 100 pf analog input: demodd v demodd dc input voltage level 100 k w resistor external to agnd - v agnd - v v i(p-p) data input voltage level (peak-to-peak value) input via a 10 nf capacitor 200 250 600 mv v i(p-p) sat input voltage level (peak-to-peak value) 50 -- mv z i input impedance 1 -- m w
1997 jan 28 31 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 package outlines unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 18.1 17.7 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot136-1 x 14 28 w m q a a 1 a 2 b p d h e l p q detail x e z c l v m a e 15 1 (a ) 3 a y 0.25 075e06 ms-013ae pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.71 0.69 0.30 0.29 0.050 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale so28: plastic small outline package; 28 leads; body width 7.5 mm sot136-1 95-01-24 97-05-22
1997 jan 28 32 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.4 0.3 0.18 0.12 7.1 6.9 0.8 9.15 8.85 0.9 0.5 7 0 o o 0.25 0.1 1.0 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot358 -1 95-12-19 97-08-04 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.9 0.5 d b p e q e a 1 a l p detail x l (a ) 3 b 8 c d h b p e h a 2 v m b d z d a z e e v m a x 1 32 25 24 17 16 9 y pin 1 index w m w m 0 2.5 5 mm scale lqfp32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm sot358-1
1997 jan 28 33 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all qfp and so packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference manual (order code 9398 510 63011). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering qfp wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). so wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. m ethod (qfp and so) during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 jan 28 34 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1997 jan 28 35 philips semiconductors product speci?cation data processor for cellular radio (dproc2) UMA1002 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca53 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2870, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580/xxx france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 437027/00/04/pp36 date of release: 1997 jan 28 document order number: 9397 750 01602

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